Seven Segment Decoder
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Rodion:
a fun (and different!) problem; thanks!
There is one small issue with the description: the segments e and f are switched in the diagram. It should go, I believe:
aaaaaa
f b
f b
f b
gggggg
e c
e c
e c
dddddd
The wikipedia article agrees with the schema above, as does the checker.
Cheers,
V.
P.S. Added my own solution to The Shredder Conundrum.
Oh my, what a shame, surely they just follow clockwise pattern :))) thanks for quick hint, fixed!
To avoid frustration when solving, please take note of this: 'so use "intermediate" signals naming them with a letter and, optionally, single digit.'
Mathias, sorry for this inconvenience. The line you suggested in emphasized in bold now.
It seems not difficult to make parser work with nested functions but I realized deduplication for them is necessary then and thought it is not needed...
However these are my first baby-steps in creating descriptive syntax for similar tasks (I hope I can come up with few more) so your objection is quite valuable and I'll try harder next time :)
BTW I'm a bit surprised already about results of 7 and 8. However, if I understand correctly, there is no simple way (and perhaps no any way at all) to prove is solution minimal or not yet?
Hi Rodion,
No need for any apology.
Reading the problem statement carefully is part of the challenge, and I jumped ahead too fast.
I just thought to point it out for others.
And no need for nested functions; my issue was that I initially used longer names such as nx1 (for not x1) for the intermediate signals.
The 7 chip answer isn’t the result of a complex optimisation algorithm but I rather used a pretty standard approach to reducing Boolean expressions.
Did it manually, and then checked via python.
The eight chip solution is generated by an algorithm, using a couple of optimizations that I came up with when solving the problem manually. There are other, reasonably straightforward, ways to add more (automatic) optimization, but I doubt I'll have time to implement them.
That's cool! I believe there are ready solutions for algorithmic optimizations (most probably they could be found among the set of tools used for programming programmable logic chips), but probably this is not the only way. I hope to check bit later (hopefully earlier than I'm retired) if describing this task in prolog may help...
Thanks for another really entertaining problem. I was aware that Boolean Algebra can be used to solve problems like this but would have to spend some time learning the techniques in order to use it. I followed the same route as Vladimir and wrote a program to design the circuit. This was probably more fun than learning Boolean Algebra!
Just noticed: after the correction of the e and f segments in the diagram, the two examples next to it also need updating.
Aha, that works :)
Thank you, Mathias :) I remember reading your note first time but slowpoking on what's wrong and then unluckily forgetting - Fixed now!